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features ? 3000 dhrystone 2.1 mips at 1.3 ghz selectable bus clock (30 cp u bus dividers up to 28x) selectable mpx/60x interf ace voltage (1.8v, 2.5v) p d typically 18w at 1.33 ghz at v dd = 1.3v; 8.0w at 1 ghz at v dd = 1.1v full operating conditions nap, doze and sleep power saving modes superscalar (four instructions fetched per clock cycle) 4 gb direct addressing range virtual memory: 4 hexabytes (2 52 ) 64-bit data and 36-bit address bus interface integrated l1: 32 kb instruction and 32 kb data cache integrated l2: 512 kb 11 independent execution units and 3 register files write-back and write-through operations f int max = 1.33 ghz (1.42 ghz to be confirmed) f bus max = 133 mhz/166 mhz description the pc7447a host processor is a high-performa nce, low-power, 32-bit implementa- tions of the powerpc reduced instruction set computer (risc) architecture combined with a full 128-bit implementation of freescale ? ?s altivec ? technology. this microprocessor is ideal for leading-edge embedded computing and signal pro- cessing applications. the pc7447a features 512 kb of on-chip l2 cache. the pc7447a microprocessor has no backside l3 cache, allowing for a smaller package designed as a pin-for-pin replacement for the pc7447 microprocessor. this device benefits from a silicon-on-insulator (soi) cmos process technology, engineered to help deliver tremendous power savings without sacrificing speed. a low-power version of the pc7447a microprocessor is also available. figure 1-1 shows a block diagram of the pc 7447a. the core is a high-performance superscalar design supporting a double-precision floating-point unit and a simd multi- media unit. the memory storage subsystem supports the mpx bus protocol and a subset of the 60x bus protocol to the main memory and other system resources. note that the pc7447a is a footprint-compatible, drop-in replacement in a pc7447 application if the core power supply is 1.3v. screening full military te mperature range (t j = -55 c, +125 c) industrial temperature range (t j = -40 c, +110 c) gh suffix hitce 360 powerpc ? 7447a risc microprocessor pc7447a preliminary rev. 5387b?hirel?07/05
2 5387b?hirel?07/05 pc7447a [preliminary] 1. block diagram figure 1-1. pc7447a microproce ssor block diagram additional features time base counter/decrementer clock multiplier jtag/cop interface thermal/power management performance monitor dynamic frequency switching (dfs) temperature dioder + x fpscr fpscr pa + x instruction unit instruction queue (12-word) 96-bit (3 instructions) reservation 32-bit floating- point unit 64-bit load/store unit (ea calculation) finished 32-bit completion unit (16-entry) 36-bit 64-bit stations (2) fpr file 16 rename buffers gpr file 16 rename buffers vr file 16 rename buffers 64-bit 128-bit 128-bit completes up srs (shadow) 128-entry itlb stores load miss ctr lr vector touch engine 32-bit ea l1 castout status l2 store queue (l2sq) vector fpu vector integer unit 1 vector integer unit 2 vector permute unit status block 1 (32-byte) memory subsystem snoop push/ interventions l1 castouts bus accumulator l1 push (4) to three per clock instructions l1 load queue (llq) l1 load miss (5) instruction fetch (2) cacheable store request (1) l1 service queues l1 store queue (lsq) l2 prefetch (3) address bus data bus castout queue (9) / push queue (10) 2 bus store queue load queue (11) completion queue reservation station reservation station reservation station reservation station branch processing unit btic (128-entry) bht (2048-entry) vr issue (4-entry/2-issue) gpr issue (6-entry/3-issue) fpr issue (2-entry/1-issue) fetcher dispatch unit instruction mmu ibat array data mmu dbat array 128-bit (4 instructions) tags 32-kbyte i cache 32-kbyte d cache tags srs (original) 128-entry dtlb reservation stations (2-entry) vector touch queue completed stores 512-kbyte unified l2 cache controller line tags block 0 (32-byte) system bus interface notes: the castout queue and push queue share resources such for a combined total of entries. the castout queue itself is limited to 9 entries, ensuring 1 entry will be available for a push. integer unit 2 reservation stations (2) reservation station integer unit 1 (3) +
3 5387b?hirel?07/05 pc7447a [preliminary] 2. general parameters table 2-1 provides a summary of the general parameters of the pc7477a. 3. features this section summarizes features of the pc7447a implementation of the powerpc architecture. major features of the pc7447a are as follows: high-performance, superscalar microprocessor ? up to four instructions can be fetched from the instruction cache at a time ? up to 12 instructions can be in the instruction queue (iq) ? up to 16 instructions can be at some stage of execution simultaneously ? single-cycle execution for most instructions ? one instruction per clock cycle throughput for most instructions ? seven-stage pipeline control eleven independent execution units and three register files ? branch processing unit (bpu) features static and dynamic branch prediction 128-entry (32-set, four-way set-associative) branch target instruction cache (btic), a cache of branch instructions that have been encountered in branch/loop code sequences. if a target instruction is in the btic, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. typically, a fetch that hits the btic provides the first four instructions in the target stream. 2048-entry branch history table (bht) with two bits per entry for four levels of prediction: not taken, strongly not taken, taken, and strongly taken up to three outstanding speculative branches branch instructions that do not update the count register (ctr) or link register (lr) are often removed from the instruction stream table 2-1. device parameters parameter description technology 0.13 m cmos, nine-layer metal die size 8.51 mm 9.86 mm transistor count 48.6 million logic design fully-static packages surface mount 360 ceramic ball grid array (hitce) core power supply 1.3v 50 mv dc nominal i/o power supply 1.8v 5% dc, or 2.5v 5% dc
4 5387b?hirel?07/05 pc7447a [preliminary] eight-entry link register stack to predict the target address of branch conditional to link register (bclr) instructions ? four integer units (ius) that share 32 gprs for integer operands three identical ius (iu1a, iu1b, and iu1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions. iu2 executes miscellaneous instructions including the cr logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions. ? five-stage fpu and a 32-entry fpr file fully ieee 754-1985-compliant fpu for both single- and double-precision operations supports non-ieee mode for time-critical operations hardware support for denormalized number thirty-two 64-bit fprs for single- or double-precision operands ? four vector units and 32-entry vector register file (vrs) vector permute unit (vpu) vector integer unit 1 (viu1) handles short-latency altivec? integer instructions, such as vector add instructions (for example, vaddsbs, vaddshs, and vaddsws). vector integer unit 2 (viu2) handles longer-latency altivec integer instructions, such as vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and vmladduhm). vector floating-point unit (vfpu) ? three-stage load/store unit (lsu) supports integer, floating-point, and vector instruction load/store traffic four-entry vector touch queue (vtq) supports all four architectures of the altivec data stream operations three-cycle gpr and altivec load latency (b yte, half word, word, vector) with one- cycle throughput four-cycle fpr load latency (single, double) with one-cycle throughput no additional delay for misaligned access within double-word boundary
5 5387b?hirel?07/05 pc7447a [preliminary] dedicated adder calculates effective addresses (eas) supports store gathering performs alignment, normalization, and prec ision conversion for floating-point data executes cache control and tlb instructions performs alignment, zero padding, and sign extension for integer data supports hits under misses (multiple outstanding misses) supports both big- and little-endian modes, including misaligned little-endian accesses three issue queues, fiq, viq, and giq, can accept as many as one, two, and three instructions, respectively, in a cycle. instruction dispatch requires the following: ? instructions can only be dispatched from the three lowest iq entries: iq0, iq1, and iq2 ? a maximum of three instructions can be dispatched to the issue queues per clock cycle ? space must be available in the cq for an instruction to dispatch (this includes instructions that are assigned a space in the cq but not in an issue queue) rename buffers ? 16 gpr rename buffers ? 16 fpr rename buffers ? 16 vr rename buffers dispatch unit ? decode/dispatch stage fully decodes each instruction completion unit ? the completion unit retires an instruction from the 16-entry completion queue (cq) when all instructions ahead of it have been completed, the instruction has finished execution, and no exceptions are pending ? guarantees sequential programming model (precise exception model) ? monitors all dispatched instructions and retires them in order ? tracks unresolved branches and flushes instructions after a mispredicted branch ? retires as many as three instructions per clock cycle separate on-chip l1 instruction and data caches (harvard architecture) ? 32-kbyte, eight-way set-associative instruction and data caches ? pseudo least-recently-used (plru) replacement algorithm ? 32-byte (eight-word) l1 cache block ? physically indexed/physical tags ? cache write-back or write-through operation programmable on a per-page or per- block basis
6 5387b?hirel?07/05 pc7447a [preliminary] ? instruction cache can provide four inst ructions per clock cycle; data cache can provide four words per clock cycle ? caches can be disabled in software ? caches can be locked in software ? mesi data cache coheren cy maintained in hardware ? separate copy of data cache tags for efficient snooping ? parity support on cache and tags ? no snooping of instruction cache except for icbi instruction ? data cache supports altivec lru and transient instructions ? critical double- and/or quad-word forwarding is performed as needed. critical quad- word forwarding is used for altivec loads and instruction fetches. other accesses use critical double-word forwarding. level 2 (l2) cache interface ? on-chip, 512-kbyte, eight-way set-associative unified instruction and data cache ? fully pipelined to provide 32 bytes per clock cycle to the l1 caches ? a total nine-cycle load latency for an l1 data cache miss that hits in l2 ? cache write-back or write-through operation programmable on a per-page or per- block basis 64-byte, two-sectored line size ? parity support on cache separate memory management units (mmus) for instructions and data ? 52-bit virtual address, 32- or 36-bit physical address ? address translation for 4-kbyte pages, variable-sized blocks, and 256-mbyte segments ? memory programmable as write-back/write-through, caching-inhibited/caching- allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis ? separate ibats and dbats (eight each) also defined as sprs ? separate instruction and data translation look aside buffers (tlbs) both tlbs are 128-entry, two-way set-associative, and use a lru replacement algorithm tlbs are hardware- or software-reloadable (that is, a page table search is performed in hardwar e or by system software on a tlb miss). efficient data flow ? although the vr/lsu interface is 128 bits, the l1/l2 bus interface allows up to 256 bits ? the l1 data cache is fully pipelined to provide 128 bits/cycle to or from the vrs ? l2 cache is fully pipelined to provide 256 bits per processor clock cycle to the l1 cache ? as many as eight outstanding, out-of-order, cache misses are allowed between the l1 data cache and the l2 bus ? as many as 16 out-of-order transactions can be present on the mpx bus
7 5387b?hirel?07/05 pc7447a [preliminary] ? store merging for multiple store misses to the same line. on ly coherency action taken (address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed) ? three-entry finished store queue and five-entry completed store queue between the lsu and the l1 data cache ? separate additional queues for efficient buffering of outbound data (such as castouts and write-through stores) from the l1 data cache and l2 cache multiprocessing support features include the following: ? hardware-enforced, mesi cache coherency protocols for data cache ? load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations power and thermal management ? a new dynamic frequency switching (dfs) feature allows the processor core frequency to be halved through software to reduce power consumption ? the following three power-saving modes are availabl e to the system: nap: instruction fetching is halted. only the clocks for the time base, decrementer, and jtag logic remain running. the part goes into the doze state to snoop memory operations on the bus and then back to nap using a qreq/qack processor-system handshake protocol. sleep: power consumption is further redu ced by disabling bus snooping, leaving only the pll in a locked and running state. all internal functional units are disabled. deep sleep: when the part is in the deep sleep state, the system can disable the pll. the system can then disable the sysclk source for greater system power savings. power-on reset procedures for restarting and relocking the pll must be followed upon exiting the deep sleep state. ? instruction cache throttling provides control of instruction fetching to limit device temperature ? a new temperature diode that can determine the temperature of the microprocessor performance monitor can be used to help debug system designs and improve software efficiency in-system testability and de bugging features through jtag boundary-scan capability testability ? lssd scan design ? ieee 1149.1 jtag interface ? array built-in self test (abist), factory test only reliability and serviceability ? parity checking on system bus ? parity checking on the l1 and l2 caches
8 5387b?hirel?07/05 pc7447a [preliminary] 4. signal description figure 4-1. pc7447a microprocessor signal groups note: for the pc7447a, there are 5 pll_cfg signals, (pll_cfg[0:4] 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 4 1 1 1 1 1 1 1 1 pc7447a int smi mcp sreset hreset ckstp_in ckstp_out tben qreq qack bvsel bmode[0:1] pmon_in pmon_out sysclk pll_cfg[0:3] (2) pll_ext ext_qual clk_out tck tdi tdo tms trst br bg a[0:35] ap[0:4] ts tt[0:4] tbst tsiz[0:2] gbl wt ci aack artry shd0/shd1 hit dbg dti[0:3] drdy d[0:63] dp[0:7] ta tea 1 1 36 5 1 5 1 3 1 1 1 1 1 2 1 1 4 1 64 8 1 1 address arbitration address transfer address transfer attributes address transfer termination data arbitration data transfer data transfer termination interrupts/resets processor status/control clock control test interface (jtag) av dd gnd v dd ov dd
9 5387b?hirel?07/05 pc7447a [preliminary] 5. detailed specification this specification describes t he specific requirements for the microprocessor pc7447a in com- pliance with atmel standard screening. 6. applicable documents 1. mil-std-883: test methods and procedures for electronics 2. mil-prf-38535: appendix a: general specifications for microcircuits the microcircuits are in accordance with the applicable documents and as specified herein. 6.1 design and construction 6.1.1 terminal connections depending on the package, the terminal connections are as shown in table 8-1 , table 6-2 and figure 4-1 . 6.2 absolute maximum ratings the tables in this section describe the pc7447a dc electrical characteristics. table 6-1 pro- vides the absolute maximum ratings . notes: 1. functional and tested operating conditions are given in table 6-2 on page 10 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guarantee d. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: v dd /av dd must not exceed ov dd by more than 1v during normal operation; this limit may be exceeded for a maxi- mum of 20 ms during the power-on reset and power-down sequences. 3. caution: ov dd must not exceed v dd /av dd by more than 2v during normal operation; this limit may be exceeded for a maxi- mum of 20 ms during the power-on reset and power-down sequences. 4. bvsel must be set to 0, such that the bus is in 1.8v mode. 5. bvsel must be set to hreset or 1, su ch that the bus is in 2.5v mode. 6. caution: v in must not exceed ov dd by more than 0.3v at any time including during power-on reset. 7. v in may overshoot/undershoot to a voltage and for a maximum duration shown in figure 6-1 on page 10 . table 6-1. absolute maximum ratings (1) symbol characteristic maximum value unit v dd (2) core supply voltage -0.3 to 1.60 v av dd (2) pll supply voltage -0.3 to 1.60 v ov dd (3)(4) processor bus supply voltage bvsel = 0 -0.3 to 1.95 v ov dd (3)(5) bvsel = hreset or ov dd -0.3 to 2.7 v v in (6)(7) input voltage processor bus -0.3 to ov dd + 0.3 v v in jtag signals -0.3 to ov dd + 0.3 v t stg storage temperature range -55 to 150 c
10 5387b?hirel?07/05 pc7447a [preliminary] 6.3 recommended op erating conditions table 6-2 provides the recommended operating conditions for the pc7447a. notes: 1. these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. 2. this voltage is the input to the filter discussed in section ?pll power supply filtering? on page 37 and not necessarily the voltage at the av dd pin, which may be reduced from v dd by the filter. figure 6-1. overshoot/undershoot voltage the pc7447a provides several i/o voltages to support both com patibility with existing systems and migration to future systems. the pc7447a core voltage must always be provided at a nom- inal 1.3v (see table 6-2 on page 10 for the actual recommended core voltage). the input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal hreset. t he output voltage will swing fr om gnd to the maximum volt- age applied to the ovdd power pins. table 6-3 on page 11 provides the input threshold voltage settings. because these settings may change in future products, it is recommended that bvsel be configured using resistor options, jumpers, or some other flexible means, with the capability to reconfigure the termination of this signal in the future if necessary. table 6-2. recommended operating conditions (1) symbol characteristic recommended value unit min max v dd core supply voltage 1.3v 50 mv or 1.1v 50 mv v av dd (2) pll supply voltage 1.3v 50 mv or 1.1v 50 mv v ov dd processor bus supply voltage bvsel = 0 1.8v 5% v ov dd bvsel = hreset or ov dd 2.5v 5% v in input voltage processor bus gnd ov dd v v in jtag signals gnd ov dd t j die-junction temperature -55 125 c c gnd gnd ? 0.3v gnd ? 0.7v not to exceed 10% of t sysclk ov dd + 20% ov dd + 5% ov dd v ih v il
11 5387b?hirel?07/05 pc7447a [preliminary] notes: 1. caution: the input threshold selection must agree with the ov dd voltages supplied. see notes in table 6-1 on page 9 . 2. if used, pull-down resistors should be less than 250 ? . 6.4 thermal characteristics 6.4.1 package characteristics notes: 1. see ?thermal management information? on page 12 for details about thermal management. 2. junction temperature is a function of on -chip power dissipation, package thermal resistance, mounting site (board) tempera- ture, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 3. per semi g38-87 and jedec jesd51-2 wit h the single-layer board horizontal. 4. per jedec jesd51-6 with the board horizontal. 5. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 6. this is the thermal resistance between the die and the case top surface as measured with the cold plate method (mil spec-883 method 1012.1) with the calculated ca se temperature. the actual value of r jc for the part is less than 0.1 c/w. 6.4.2 internal package conduction resistance for the exposed-die packaging technology described in table 6-4 on page 11 , the intrinsic con- duction thermal resistance paths are as follows: the die junction-to-case thermal resistance (the case is actually the top of the exposed silicon die) the die junction-to-ball thermal resistance figure 19 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. table 6-3. input threshold voltage setting (1) bvsel signal processor bus input threshold is relative to: notes 01.8v (2) ?hreset not available hreset 2.5v 12.5v table 6-4. package thermal characteristics (1) symbol characteristic value unit r ja (2)(3) junction-to-ambient thermal resistance, natural convection, single-layer (1s) board 26 c/w r jma (2)(4) junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board 19 c/w r jma (2)(4) junction-to-ambient thermal resistance, 200 ft ./min. airflow, single-layer (1s) board 20 c/w r jma (2)(4) junction-to-ambient thermal resistance, 200 ft ./min. airflow, four-layer (2s2p) board 16 c/w r jb (5) junction-to-board thermal resistance 10 c/w r jc (6) junction-to-case ther mal resistance < 0.1 c/w
12 5387b?hirel?07/05 pc7447a [preliminary] figure 6-2. c4 package with heat sink mounted to a printed-circuit board note the internal versus external package resistance. heat generated on the active si de of the chip is co nducted through the s ilicon, through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. because the silicon thermal resist ance is quite small, the temper ature drop in t he silicon may be neglected for a first-order analysis. thus, the thermal interface material and the heat sink con- duction/convective thermal resistances are the dominant terms. 6.4.3 thermal management information this section provides thermal management informa tion for the high coefficient of the thermal expansion ceramic ball grid array (hitce) package for air-cooled applications. proper thermal control design is primarily dependent on the system-level design ? the heat sink, airflow, and thermal interface material. the pc7447a implem ents several features designed to assist with thermal management, including dfs and the temperature diode. dfs reduces the power con- sumption of the device by reducing the core frequency; see table 6-6 on page 19 for specific information regarding power reduction and dfs. the temperature diode allows an external device to monitor the die temperature in order to detect excessive temperature conditions and alert the system; see section ?temperature diode? on page 16 for more information. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods ? spring clips to holes in the printed-circuit board or package, and mounting clips and screw assembly (see figure 6-3 ); however, due to the potentially large mass of the heat sink, attachment through the printed-circuit board is suggested. if a spring clip is used, the spring force should not exceed ten pounds. external resistance external resistance internal resistance radiation convection heat sink thermal interface material die/package die junction package/leads printed-circuit board radiation convection
13 5387b?hirel?07/05 pc7447a [preliminary] figure 6-3. package exploded cross-sectional view with several heat sink options 6.4.4 thermal inte rface materials a thermal interface material is recommended at the package lid-to-heat sink interface to mini- mize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 6-4 on page 14 shows the thermal performance of three thin- sheet thermal-interface materials (silicone, graphi te/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing con- tact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. often, heat sinks are attached to the package by means of a spring clip to holes in the printed- circuit board (see figure 6-3 on page 13 ). therefore, synthetic grease offers the best thermal performance, considering the low interface pressure, and is recommended due to the high power dissipation of the pc7447a. of course, the selection of any thermal interface material depends on many factors ? thermal performance requirements, manufacturability, service tem- perature, dielectric properties, cost, and so on. printed-circuit board thermal interface material heat sink clip heat sink hcte package
14 5387b?hirel?07/05 pc7447a [preliminary] figure 6-4. thermal performance of select thermal interface material 6.4.4.1 heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t i + t r + (r jc + r int + r sa ) p d where: t j is the die-junction temperature t i is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet r jc is the junction-to-ca se thermal resistance r int is the adhesive or interface material thermal resistance r sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device 0 0.5 1 1.5 2 010 20304050607080 silicone sheet (0.006 in.) bare joint floroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
15 5387b?hirel?07/05 pc7447a [preliminary] during operation, the die-junction temperatures (t j ) should be maintained less than the value specified in table 6-2 on page 10 . the temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t i ) may range from 30 to 40 c. the air tem- perature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the thermal interface material (r int ) is typically about 1.5 c/w. for example, assuming a t i of 30 c, a t r of 5 c, an hitce package r jc = 0.1, and a typical power consumption (p d ) of 18.7w, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.1 c/w + 1.5 c/w + sa ) 18.7w for this example, a r sa value of 2.1 c/w or less is required to main tain the die junction temper- ature below the maximum value of table 6-2 on page 10 . though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a com- mon figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise cautio n when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. the final die-junction operating temper ature is not only a function of the component- level thermal resistance, but the system-level de sign and its operating conditions. in addition to the component's power consumption, a number of factors affect the final operating die-junction temperature ? airflow, board population (local heat fl ux of adjacent components), heat sink effi- ciency, heat sink attach, heat sink placemen t, next-level interconnect technology, system air temperature rise, altitude, and so on. due to the complexity and variety of syste m-level boundary conditions for today's microelec- tronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level designs. for system thermal modeling, the pc7447a thermal model is shown in figure 6-5 on page 16 . four volumes represent this device. two of the volumes, solder ball-air and substrate, are mod- eled using the package outline si ze of the package. th e other two, die, and bump-underfill, have the same size as the die. the silicon die should be modeled 9.5 9.5 0.7 mm with the heat source applied as a uniform sour ce at the bottom of the volume . the bump and underfill layer is modeled as 7.3 9.3 0.7 mm (or as a collapsed volume) with orthotropic material properties: 0.6 w/(m k) in the xy-plane and 1.9 w/(m k) in the direction of the z-axis. the substrate vol- ume is 25 25 1.2 mm, and has 8.1 w/(m k) isotropic conductivity in the xy-plane and 4 w/(m k) in the direction of the z-axis. the solder ball and air layer are modeled with the same horizontal dimensions as the substrate and are 0.6 mm thick. they can also be modeled as a collapsed volume using orthotropic material properties: 0.034 w/(m k) in the xy-plane direction and 3.8 w/(m k) in the direction of the z-axis.
16 5387b?hirel?07/05 pc7447a [preliminary] figure 6-5. recommended thermal model of pc7447a 6.4.4.2 temperature diode the pc7447a has a temperature diode on the microprocessor that can be used in conjunction with other system temperature mo nitoring devices. these devices use the negative temperature coefficient of a diode operated at a constant cu rrent to determine the temperature of the micro- processor and its environment. for proper oper ation, the monitoring device used should auto- calibrate the device by canceling out the v be variation of each pc7447a?s internal diode. the following are the specifications of the pc7447a on-board temperature diode: v f > 0.40v v f < 0.90v operating range 2 - 300 a diode leakage < 10 na at 125 c ideality factor over 5 a ? 150 a at 60 c: 1 <= n <= tbd ideality factor is defined as the deviation from the ideal diode equation: another useful equation is: bump and underfill die substrate solder and air die substrate side view of model (not to scale) side view of model (not to scale) x y z conductivity value unit bump and underfill (7.3 x 9.3 x 0.070 mm) w/(m x k) substrate (25 x 25 x 1.2 mm) solder ball and air (25 x 25 x 0.6 mm) k x 0.6 k y 0.6 k z 1.9 k x 8.1 k y 8.1 k z 4.0 k x k y k z 0.034 0.034 3.8 i fw i s e qv f nkt ---------- - 1 ? = v h v l ? n kt q ------- in i h i l ----- =
17 5387b?hirel?07/05 pc7447a [preliminary] where: i fw = forward current i s = saturation current v d = voltage at diode v f = voltage forward biased v h = diode voltage while i h is flowing v l = diode voltage while i l is flowing i h = larger diode bias current i l = smaller diode bias current q = charge of electron (1.6 10 -19 c) n = ideality factor (normally 1.0) k = boltzman?s constant (1.38 10 -23 joules/k) t = temperature (kelvins) the ratio of i h to i l is usually selected to be 10:1. the above simplifie s to the following: v h - v l = 1.986 10 -4 nt solving for t, the equation becomes: 6.4.4.3 dynamic frequency switching (dfs) the new dfs feature in the pc7447a adds the ability to divide the processor-to-system bus ratio by two during normal functional operation by setting the hid1[dfs1] bit. the frequency change occurs in 1 clock cycle, and no idle waiting period is required to switch between modes. additional information regarding dfs can be found in the mpc7450 risc microprocessor fam- ily user?s manual. 6.4.4.4 power consumption with dfs enabled power consumption with dfs enabled can be approximated using the following formula: where: p dfs = power consumption with dfs enabled f dfs = core frequency with dfs enabled f = core frequency prior to enabling dfs p = power consumption prior to enabling dfs (see table 6-6 on page 19 ) p ds = deep sleep mode power consumption (see table 6-6 on page 19 ) the above is an approximation only. power consumption with dfs enabled is not tested or guaranteed. nt v h v ? l 1 986 10 4 ? , --------------------------------- = p dfs f dfs f ---------- - pp ds ? () p ds + =
18 5387b?hirel?07/05 pc7447a [preliminary] 6.4.4.5 bus-to-core multip lier constraints with dfs dfs is not available for all bu s-to-core multipliers as confi gured by pll_cfg[0:4] during hard reset. specifically, because the pc7447a does not support quarter clock ratios or the 1x multi- plier, the dfs feature is limited to integer pll multipliers of 4x and higher. the complete listing is shown in table 6-5 on page 18 . table 6-5. valid divide ratio configurations bus-to-core mu ltiplier configured by pll_cfg[0:4] (see table 13-1 on page 35 ) bus-to-core mu ltiplier with hid1[dfs1] = 1 ( 2) 2x n/a 3x n/a 4x 2x 5x 2.5x 5.5x 2x 6x 3x 6.5x n/a 7x 3.5x 7.5x n/a 8x 4x 8.5x n/a 9x 4.5x 9.5x n/a 10x 5x 10.5x n/a 11x 5.5x 11.5x n/a 12x 6x 12.5x n/a 13x 6.5x 13.5x n/a 14x 7x 15x 7.5x 16x 8x 17x 8.5x 18x 9x 20x 10x 21x 10.5x 24x 12x 28x 14x
19 5387b?hirel?07/05 pc7447a [preliminary] 6.4.4.6 minimum core frequency requirements with dfs in many systems, enabling dfs can result in very low processor core frequencies. however, care must be taken to ensure that the resulting processor core frequency is within the limits specified in table 9-2 on page 25 . proper operation of the device is not guaranteed at core fre- quencies below the specified minimum f core . 6.4.5 power consumption table 7 provides the power consumption for the pc7447a. for information regarding power consumption when dynamic frequency switching is enabled, see ?dynamic frequency switch- ing (dfs)? on page 17. . notes: 1. these values apply for all valid processor buses. the values do not include i/o supply power (ov dd ) or pll supply power (av dd ). ov dd power is system dependent but is typically < 5% of v dd power. worst case power consumption for av dd < 3mw. 2. typical power is an average value measured at the nominal recommended v dd (see table 6-2 on page 10 ) and 65 c while running the dhrystone 2.1 be nchmark and achieving 2.3 dhrystone mips/mhz 3. maximum power is the average measured at nominal v dd and maximum operating junction temperature (see table 6-2 on page 10 ) while running an entirely cache-resident, contrived seq uence of instructions which keep all the execution units maximally busy. 4. doze mode is not a user-definable state; it is an intermed iate state between full-power and ei ther nap or sleep mode. as a result, power consumption for this mode is not tested. 5. power consumption for these devices is artificially constr ained during screening to assure lower power consumption than other speed grades. table 6-6. power consumption for pc7447a processor (cpu) frequency 1000 1167 1267 1333 (5) 1420 unit full-power mode core power supply 1.1 1.1 1.3 1.3 1.3 typical (1)(2) 8 9.2 18.3 18 21 w maximum (1)(3) 26 25 30 w nap mode 11.5 13 typical (1)(2) 1.3 1.3 4.1 3.3 4.1 w sleep mode typical (1)(2) 1.3 1.3 4.1 3.3 4.1 w deep sleep mode (pll disabled) typical (1)(2) 1.2 1.2 4 3.2 4 w
20 5387b?hirel?07/05 pc7447a [preliminary] 7. pin assignment figure 7-1 shows the pinout of the pc7447a, 360 high coefficient of the thermal expansion ceramic ball grid array (hitce) package as viewed from the top surface. figure 7-2 shows the side profile of the hitce package to indicate the direction of the top surface view. figure 7-1. pinout of the pc7447a, 360 hitce pack age as viewed from the top surface figure 7-2. side view of the cbga package a b c d e f g h j k l m n p r t 3 2 1456 16 17 18 19 u v w 15 14 13 12 11 10 9 8 7 substrate assembly encapsulant view die
21 5387b?hirel?07/05 pc7447a [preliminary] 8. pinout listings table 8-1 provides the pinout listing for the pc7447a, 360 hitce package. the pinouts of the pc7447a and pc7447 are pin compatible but there have been some changes. a pc7447a may be populated on a board designed for a pc7447 provided all pins defined as ?not connected? for the pc7447 are unterminated as required by t he pc7457 risc microprocessor specification. the pc7447a uses pins previously marked ?not connected? for the temperature diode pins and for additional power and ground connections. because these ?not connected? pins in the pc7447 360 pin package are not driven in functional mode, a pc7447 can be populated in a pc7447a board. see section ?connection recommendations? on page 37 for additional information. note: this pinout is not compatible with th e pc750, pc7400, or pc7410 360 bga package. table 8-1. pinout listing for the pc7447a, 360 hitce package signal name pin number active i/o i/f select (1) a[0:35] (2) e11, h1, c11, g3, f10, l2, d11, d1, c10, g2, d12, l3, g4, t2, f4, v1, j4, r2, k5, w2, j2, k4, n4, j3, m5, p5, n3, t1, v2, u1, n5, w1, b12, c4, g10, b11 high i/o bvsel aack r1 low input bvsel ap[0:4] (2) c1, e3, h6, f5, g7 high i/o bvsel artry (3) n2 low i/o bvsel av dd a8 ? input bvsel bg m1 low input bvsel bmode0 (4) g9 low input bvsel bmode1 (5) f8 low input bvsel br d2 low output bvsel bvsel (1)(6) b7 high input bvsel ci (3) j1 low output bvsel ckstp_in a3 low input bvsel ckstp_out b1 low output bvsel clk_out h2 high output bvsel d[0:63] r15, w15, t14, v16, w16, t15, u15, p14, v13, w13, t13, p13, u14, w14, r12, t12, w12, v 12, n11, n10, r11, u11, w11, t11, r10, n9, p10, u10, r9, w10, u9, v9, w5, u6, t5, u5, w7, r6 , p7, v6, p17, r19, v18, r18, v19, t19, u19, w19, u18, w17, w18, t16, t18, t17, w3, v17, u4, u8, u7, r7, p6, r8, w8, t8 high i/o bvsel dbg m2 low input bvsel dp[0:7] t3, w4, t4, w9, m6, v3, n8, w6 high i/o bvsel drdy (7) r3 low output bvsel dti[0:3] (8) g1, k1, p1, n1 high input bvsel ext_qual (9) a11 high input bvsel gbl e2 low i/o bvsel
22 5387b?hirel?07/05 pc7447a [preliminary] gnd b5, c3, d6, d13, e17, f3, g17, h4, h7, h9, h11, h13, j6, j8, j10, j12, k7, k3, k9, k11, k13, l6, l8, l10, l12, m4, m7, m9, m11, m13, n7, p3, p9, p12, r5, r14, r17, t7, t10, u3, u13, u17, v5, v8, v11, v15 ?? n/a gnd (15) a17, a19, b13, b16, b18, e12, e19, f13, f16, f18, g19, h18, j14, l14, m15, m17, m19, n14, n16, p15, p19 ?? n/a gnd_sense (19) g12, n13 ? ? n/a hit (7) b2 low output bvsel hreset d8 low input bvsel int d4 low input bvsel l1_tstclk (9) g8 high input bvsel l2_tstclk (10) b3 high input bvsel no connect (11) a6, a14, a15, b14, b15, c14, c15, c16, c17, c18, c19, d14, d15, d16, d17, d18, d19, e14, e15, f14, f15, g14, g15, h15, h16, j15, j16, j17, j18, j19, k15, k16, k17, k18, k19, l15, l16, l17, l18, l19 ?? ? lssd_mode (6)(12) e8 low input bvsel mcp c9 low input bvsel ov dd b4, c2, c12, d5, f2, h3, j5, k2, l5, m3, n6, p2, p8, p11, r4, r13, r16, t6, t9, u2, u12, u16, v4, v7, v10, v14 ?? n/a ov dd _sense (16) e18, g18 ? ? n/a pll_cfg[0:4] b8, c8, c7, d7, a7 high input bvsel pmon_in (13) d9 low input bvsel pmon_out a9 low output bvsel qack g5 low input bvsel qreq p4 low output bvsel shd [0:1] (3) e4, h5 low i/o bvsel smi f9 low input bvsel sreset a2 low input bvsel sysclk a10 ? input bvsel ta k6 low input bvsel tben e1 high input bvsel tbst f11 low output bvsel tck c6 high input bvsel tdi (6) b9 high input bvsel tdo a4 high output bvsel tea l1 low input bvsel temp_anode (17) n18 temp_cathode (17) n19 table 8-1. pinout listing for the pc7447a, 360 hitce package (continued) signal name pin number active i/o i/f select (1)
23 5387b?hirel?07/05 pc7447a [preliminary] notes: 1. ov dd supplies power to the processor bus, jtag, and all control signals; v dd supplies power to the processor core and the pll (after filtering to become av dd ). to program the i/o voltage, connect bvsel to either gnd (selects 1.8v), or to hreset or ov dd (selects 2.5v); see table 6-3 on page 11 . if used, the pull-down resistor should be less than 250 ? . because these settings may change in future products, it is recommended bvsel be configured using resistor options, jumpers, or some other flexible means, with the capability to re configure the termination of this signal in the future if neces - sary. for actual recommended value of v in or supply voltages see table 6-2 on page 10 . 2. unused address pins must be pulled down to gnd and corresponding address parity pins pulled up to ov dd . 3. these pins require weak pull-up resistors (for example, 4.7 k ? ) to maintain the control signals in the negated state after they have been actively negated and released by the pc7447a and other bus masters. 4. this signal selects between mpx bus mode (asserted) and 60x bus mode (negated) and will be sampled at hreset going high. 5. this signal must be negated during reset, by pull-up resistor to ov dd or negation by ?hreset (inverse of hreset ), to ensure proper operation. 6. internal pull up on die. 7. ignored in 60x bus mode. 8. these signals must be pulled down to gnd if un used, or if the pc7447a is in 60x bus mode. 9. these input signals are for factory use only and must be pulled down to gnd for normal machine operation. 10. this test signal is recommended to be tied to hreset ; however, other configurations will not adversely affect performance. 11. these signals are for factory use only and must be left unc onnected for normal machine operation. some pins that were ncs on the pc7447, have now been defined for other purposes. 12. these input signals are for factory use only and must be pulled up to ov dd for normal machine operation. 13. this pin can externally cause a performance monitor event. counting of the event is enabled through software. 14. this signal must be asserted during reset, by pull down to gnd or assertion by hreset , to ensure proper operation. 15. these pins were ncs on the pc7447. they may be left unconnected for backward compat ibility with these devices, but it is recommended they be connected in new designs to facilitate future products. see section ?connection recommendations? on page 37 for more information. 16. these pins were ov dd pins on the pc7447. these pins are internally connected to ov dd and are intended to allow an exter- nal device to detect the i/o voltage level present inside the device package. if unused, they must be connected directly to ov dd or left unconnected. 17. these pins provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature of the processor. these pins may be left unterminated if unused. 18. these pins are internally connected to v dd and are intended to allow an external device to detect the processor core voltage level present inside the device package. if unused, they must be connected directly to v dd or left unconnected. 19. these pins are internally connected to gnd and are intended to allow an external device to detect the processor ground voltage level present inside the device package. if unused, th ey must be connected directly to gnd or left unconnected. note: caution must be exercised when performing boundary scan test operations on a board designed for a pc7447a but populated with an pc7447. test[0:3] (12) a12, b6, b10, e10 ? input bvsel test[4] (9) d10 ? input bvsel tms (6) f1 high input bvsel trst (6)(14) a5 low input bvsel ts (3) l4 low i/o bvsel tsiz[0:2] g6, f7, e7 high output bvsel tt[0:4] e5, e6, f6, e9, c5 high i/o bvsel wt (3) d3 low output bvsel v dd h8, h10, h12, j7, j9, j11, j13, k8 , k10, k12, k14, l7, l9, l11, l13, m8, m10, m12 ?? n/a v dd (15) a13, a16, a18, b17, b19, c13, e13, e16, f12, f17, f19, g11, g16, h14, h17, h19, m14, m16, m18, n15, n17, p16, p18 ?? n/a v dd _sense (18) g13, n12 ? ? n/a table 8-1. pinout listing for the pc7447a, 360 hitce package (continued) signal name pin number active i/o i/f select (1)
24 5387b?hirel?07/05 pc7447a [preliminary] this is because in the pc7447 it is possible to drive the latc hes associated with the former ?no connect? pins in the pc7447, potentially causing contention on those pins. to prevent this, ensu re that these pins are not connected on the board or, if the y are connected, ensure that the states of internal pc7447 latches do not cause these pins to be driven during board testing. 9. electrical characteristics 9.1 static characteristics table 9-1 provides the dc electrical characteristics for the pc7447a . notes: 1. nominal voltages; see table 6-2 on page 10 for recommended operating conditions. 2. for processor bus signals, the reference is ov dd while gv dd is the reference for the l3 bus signals. 3. excludes test signals and ieee 1149.1 boundary scan (jtag) signals. 4. the leakage is measured for nominal ov dd /gv dd and v dd , or both ov dd /gv dd and v dd must vary in the same direction (for example, both ov dd and v dd vary by either +5% or -5%). 5. capacitance is periodically sampled rather than 100% tested. 6. excludes signals with inter nal pull ups: bvsel, lssd_mode , tdi, tms, and trst . characterization of leakage current for these signals is currently being conducted. table 9-1. dc electrical specifications (see table 6-2 on page 10 for recommended operating conditions ) symbol characteristic nominal bus voltage (1) min max unit notes v ih input high voltage (all inputs) 1.8 ov dd 0.65 ov dd + 0.3 v (2) 2.5 1.7 ov dd + 0.3 v il input low voltage (all inputs) 1.8 -0.3 ov dd 0.35 v (2)(6) 2.5 -0.3 0.7 i in input leakage current, v in = gv dd /o dd v in = gnd ??30 -30 a (2)(3) i tsi high-impedance (off-state) leakage current, v in = gv dd /o dd v in = gnd ??30 -30 a (2)(3)(4) v oh output high voltage at i oh = -5 ma 1.8 ov dd - 0.45 ? v 2.5 1.8 ? v ol output low voltage at i ol = 5 ma 1.8 ? 0.45 v 2.5 ? 0.6 c in capacitance, v in = 0v f = 1 mhz all other inputs ? 8 pf (5) v ih input high voltage (all inputs) 1.8 ov dd 0.65 ov dd + 0.3 v (2) 2.5 1.7 ov dd + 0.3 v il input low voltage (all inputs) 1.8 -0.3 ov dd 0.35 v (2)(6) 2.5 -0.3 0.7 i in input leakge current, v in = gv dd /ov dd v in = gnd ??30 -30 a (2)(3)
25 5387b?hirel?07/05 pc7447a [preliminary] 9.2 dynamic characteristics this section provides the ac electrical characte ristics for the pc7447a. after fabrication, func- tional parts are sorted by maximum processor core frequency as shown in section ?clock ac specifications? on page 25 and tested for conformance to the ac specifications for that fre- quency. the processor core frequency is deter mined by the bus (sysclk) frequency and the settings of the pll_cfg[0:4] signals, and can be dynamically modified using dynamic fre- quency switching (dfs). parts are sold by maximum processor core frequency; see ?ordering information? on page 42. for information on ordering parts. dfs is described in section ?dynamic frequency switching (dfs)? on page 17 . 9.2.1 clock ac specifications table 8 provides the clock ac timing specifications as defined in figure 9-1 on page 26 and rep- resents the tested operating frequencies of the devices. the maximum system bus frequency, f sysclk , given in table 9-2 on page 25 is considered a practical ma ximum in a typical single-pro- cessor system. the actu al maximum sysclk frequency for an y application of the pc7447a will be a function of the ac timings of the pc7447a, the ac timings for the system controller, bus loading, printed-circuit board topology, trace lengths, and so forth, and may be less than the value given in table 9-2 on page 25 . table 9-2. clock ac timing specifications (see table 6-2 on page 10 for recommended operating conditions ) symbol characteristic maximum processor core frequency unit notes 1000 mhz 1267 mhz 1333 mhz 1420 mhz v dd = 1.3v v dd = 1.3v v dd = 1.3 v dd = 1.3 minmaxminmaxminmaxminmax f core processor core frequency 600 1000 600 1267 600 1333 600 1420 mhz (1)(8)(9) f vco vco frequency 1200 2000 1200 2533 1200 2667 1200 2840 mhz (1)(9) f sysclk sysclk frequency 33 167 33 167 33 167 33 167 mhz (1)(2)(8) t sysclk sysclk cycle time 6.0 30 6 30 6 30 6 30 ns (2) t kr , t kf sysclk rise and fall time ?1.0?1?1?1ns (3) t khkl /t sysclk sysclk duty cycle measured at ov dd /2 40 60 40 60 40 60 40 60 % (4) sysclk jitter (5)(6) ? 150 ? 150 ? 150 ? 150 ps (5)(6) internal pll relock time (7) ? 100 ? 100 ? 100 ? 100 s (7)
26 5387b?hirel?07/05 pc7447a [preliminary] notes: 1. caution: the sysclk fr equency and pll_cfg[ 0:4] settings must be chosen such that the resulting sysclk (bus) fre- quency, processor core frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0:4] signal description in section ?pll configuration? on page 34 for valid pll_cfg[0:4] settings. 2. assumes a lightly-loaded, single-processor system. 3. rise and fall times for the sysclk input measured from 0.4v to 1.4v. 4. timing is guaranteed by design and characterization. 5. guaranteed by design. 6. the sysclk driver?s closed loop jitter bandw idth should be less than 1.5 mhz at -3 db. 7. relock timing is guaranteed by design and characterization. pll relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on rese t sequence. this spec ification also applies when the pll has been disabled and subsequently re -enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll relock time during the power-on reset sequence. 8. caution: if dfs is ena bled, the sysclk frequency and pll_cfg[0:4] settings must be chosen such that the resulting pro- cessor frequency is greater than or equal to the minimum core frequency. 9. caution: these values specif y the maximum processor core and vco frequencie s when the device is operated at the nomi- nal core voltage. if operating the device at the derated core voltage, the processor core and vco frequencies must be reduced. figure 9-1 provides the sysclk input timing diagram. figure 9-1. sysclk input timing diagram v m = midpoint voltage (ov dd /2) 9.2.2 processor bus ac specifications table 9-3 provides the processor bus ac timing specifications for the pc7447a as defined in figure 7-2 on page 20 and figure 9-2 on page 28 .. symbol characteristic maximum processor core frequency unit notes 1000 mhz 1167 mhz v dd = 1.1v v dd = 1.1v min max min max f core processor core frequency 500 1000 500 1167 mhz (1)(8)(9) f vco vco frequency 1000 2000 1000 2233 mhz (1)(9) f sysclk sysclk frequency 33 167 33 167 mhz (1)(2)(8) t sysclk sysclk cycle time 6 30 6 30 ns (2) t kr , t kf sysclk rise and fall time ? 1 ? 1 ns (3) t khkl /t sysclk sysclk duty cycle measured at ov dd /2 40 60 40 60 % (4) sysclk jitter (5)(6) ?150?150ps (5)(6) internal pll relock time (7) ?100?100s (7) sysclk vm vm vm t khkl t sysclk cv il c v ih t kr t kf
27 5387b?hirel?07/05 pc7447a [preliminary] table 9-3. processor bus ac timing specifications (1) (at recommended operating conditions, see table 6-2 on page 10 .) symbol (2) parameter all speed grades unit min max t avkh t dvkh t ivkh t mvkh (8) input setup times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , artry , bg , ckstp_in , dbg , dti[0:3], gbl , tt[0:3], qack , ta , tben, tea , ts , ext_qual, pmon_in , shd [0:1], bmode [0:1], bvsel 1.8 1.8 1.8 1.8 ? ? ? ? ns t axkh t dxkh t ixkh t mxkh (8) input hold times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , artry , bg , ckstp_in , dbg , dti[0:3], gbl , tt[0:3], qack , ta , tben, tea , ts , ext_qual, pmon_in , shd [0:1] bmode[0:1], bvsel 0 0 0 0 ? ? ? ? ns t khav t khdv t khov output valid times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , artry , br , ci , ckstp_in , drdy , dti[0:3], gbl , hit , pmon_out , qreq, tbst , tsiz[0:2], tt[0:3], ts , shd [0:1], wt ? ? ? 2 2 2 ns t khax t khdx t khox output hold times: a[0:35], ap[0:4] d[0:63], dp[0:7] aack , artry , br , ci , ckstp_in , drdy , dti[0:3], gbl , hit , pmon_out , qreq, tbst , tsiz[0:2], tt[0:3], ts , shd [0:1], wt 0.5 0.5 0.5 ? ? ? ns t khoe (5) sysclk to output enable 0.5 ? ns t khoz (5) sysclk to output high impedance (all except ts , artry , shd0 , shd1 ) ?3.5ns t khtspz (3)(4)(5) sysclk to ts high impedance after precharge ? 1 t sysclk t kharp (3)(5)(6)(7) maximum delay to artry /shd0 /shd1 precharge ? 1 t sysclk t kharpz (3)(5)(6)(7) sysclk to artry /shd0 /shd1 high impedance after precharge ? 2 t sysclk
28 5387b?hirel?07/05 pc7447a [preliminary] notes: 1. all input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input sysclk. all output specifications are m easured from the midpoint of the rising edge of sysclk to the midpoint of the sig- nal in question. all output timings assume a purely resistive 50 ? load (see figure 7-2 on page 20 ). input and output timings are measured at the pin; time-of-fli ght delays must be added for trace lengths, vias, and connecto rs in the system. 2. the symbology used for timing specificat ions herein follows the pattern of t (signal)(state)(reference)(state) for inputs and t (reference)(state)(signal)(state) for outputs. for example, t ivkh symbolizes the time input signals (i) reach the valid state (v) relative to the sysclk reference (k) going to the hi gh (h) state or input setup time. and t khov symbolizes the time from sysclk (k) going high (h) until outputs (o) are valid (v) or output valid time . input hold time can be read as the time that the input sig nal (i) went invalid (x) with respect to the rising clock edge (kh) (note the position of the refer ence and its state for inputs) a nd output hold time can be read as the time from the rising edge (kh) until the output went invalid (ox). 3. t sysclk is the period of the external clock ( sysclk) in ns. the numbers given in the ta ble must be multiplied by the period of sysclk to compute the actual time duration (in ns) of the parameter in question. 4. according to the bus protocol, ts is driven only by the currently active bus master. it is asserted low and precharged high before returning to high impedance, as shown in figure 9-3 on page 29 . the nominal precharge width for ts is 0.5 t sysclk , that is, less than the minimum t sysclk period, to ensure that another master asserting ts on the following clock will not con- tend with the precharge. output va lid and output hold timing is tested for the sig nal asserted. output valid time is tested for precharge.the high-impedance behavior is guaranteed by design. 5. guaranteed by design and not tested. 6. according to the bus protocol, artry can be driven by multiple bus masters through the clock period immediately following aack . bus contention is not an issue because any master asserting artry will be driving it low. any master asserting it low in the first clock following aack will then go to high impedance for 1 clock before precharging it high during the second cycle after the assertion of aack . the nominal precharge width for artry is 1.0 t sysclk ; that is, it should be high impedance as shown in figure 9-3 on page 29 before the first opportunity for another master to assert artry . output valid and output hold timing is tested for the signal asserted.the high-impedance behavior is guaranteed by design. 7. according to the mpx bus protocol, shd0 and shd1 can be driven by multiple bus masters beginning the cycle of ts . tim- ing is the same as artry , that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire cycle (crossing a bus cycle boundary) before being th ree-stated again. the nominal precharge width for shd0 and shd1 is 1.0 t sysclk . the edges of the precharge vary depending on the programmed ratio of core to bus (pll configurations). 8. bmode [0:1] and bvsel are mode select inputs and are sampled before and after hreset negation. these parameters represent the input setup and hold times for each sample. th ese values are guaranteed by design and not tested. these inputs must remain stable after the second sample. see figure 9-2 on page 28 for sample timing. figure 9-2 provides the mode select input timing diagram for the pc7447a. the mode select inputs are sampled t wice, once before and once after hreset negation. figure 9-2. mode input sample timing diagram hreset mode signals v m v m v m = midpoint voltage (ovdd/2) sysclk 1st sample 2nd sample
29 5387b?hirel?07/05 pc7447a [preliminary] figure 9-3 provides the input/output ti ming diagram for the pc7447a. figure 9-3. input/output timing diagram note: vm = midpoint voltage (ov dd /2) sysclk all inputs vm all outputs vm (except ts, all outputs ts vm t khoe artry, shd0, shd1) (except ts, artry, shd0, shd1) artry, shd0, shd1 t avkh t khav t mvkh t ivkh t axkh t ixkh t mxkh t khdv t khov t khax t khdx t khox t khoz t khtspz t khtsx t khtsv t khtsv t kharv t kharp t kharx t kharpz
30 5387b?hirel?07/05 pc7447a [preliminary] 9.2.3 ieee 1149.1 ac timing specifications table 9-4 provides the ieee 1149.1 (jtag) ac timing specifications as defined in figure 9-5 through figure 9-8 on page 32 . notes: 1. all outputs are measured from the midpoint voltage of th e falling/rising edge of tclk to the midpoint of the signal in ques- tion. the output timings are measured at the pins . all output timings assume a purely resistive 50 ? load (see figure 9-4 ). time-of-flight delays must be added for trace lengths, vias and connectors in the system. 2. trst is an asynchronous level sensitive signal. the time is for test purposes only. 3. non-jtag signal input timing with respect to tck. 4. non-jtag signal output timing with respect to tck. 5. guaranteed by design and characterization figure 9-4 provides the ac test load for tdo and the boundary-scan outputs of the pc7457. figure 9-4. alternate ac test load for the jtag interface table 9-4. jtag ac timing specificatio ns (independent of sysclk) (1) at recommended operating conditions (see table 6-2 on page 10 ) symbol parameter min max unit f tclk tck frequency of operation 0 33.3 mhz t tclk tck cycle time 30 ? ns t jhjl tck clock pulse width measured at 1.4v 15 ? ns t jr and t jf tck rise and fall times ? 2 ns t trst (2) trst assert time 25 ? ns t dvjh (3) t ivjh input setup times: boundary-scan data tms, tdi 4 0 ? ? ns t dxjh (3) t ixjh input hold times: boundary-scan data tms, tdi 20 25 ? ? ns t jldv (4) t jlov valid times: boundary-scan data tdo 4 4 20 25 ns t jldx (4) t jlox output hold times: boundary-scan data tdo 30 30 ? ? t jldz (4)(5) t jloz tck to output high impedance: boundary-scan data tdo 3 3 19 9 ns output z 0 = 50 ? r l = 50 ? ov dd /2
31 5387b?hirel?07/05 pc7447a [preliminary] figure 9-5. jtag clock input timing diagram note: vm = midpoint voltage (ov dd /2) figure 9-6. trst timing diagram note: vm = midpoint voltage (ov dd /2) figure 9-7. boundary-scan timing diagram note: vm = midpoint voltage (ov dd /2) vm vm vm t tclk t jr t jf t jhjl tclk trst t trst vm vm vm tck boundary data inputs boundary data outputs boundary data outputs t dxjh t dvjh t jldv t jldz output data valid t jldx vm input data valid output data valid
32 5387b?hirel?07/05 pc7447a [preliminary] figure 9-8. test access port timing diagram note: vm = midpoint voltage (ov dd /2) 10. preparation for delivery 10.1 handling mos devices must be handled with certain precautions to avoid damage due to accumulation of static charge. input protection devices have been designed in the chip to minimize the effect of static buildup. however, the followin g handling practices are recommended: devices should be handled on benche s with conductive and grounded surfaces ground test equipment, tools and operator do not handle devices by the leads store devices in conductive foam or carriers avoid use of plastic, rubber or silk in mos areas maintain relative humidity above 50% if practical t jlox input data valid t ivjh t ixjh t jlov t jloz output data valid output data valid vm tck tdi, tms tdo tdo vm
33 5387b?hirel?07/05 pc7447a [preliminary] 11. mechanical dimensions for the pc7447a, 360 hitce figure 11-1 provides the mechanical dimensions and bottom su rface nomenclature for the pc7447a, 360 hitce package. figure 11-1. mechanical dimensions and bottom surface nomenclature for the pc7447a, 360 cbga package notes: 1. dimensioning and tolerance per asme y14.5m, 1994 2. dimensions in millimeters 3. top side a1 corner index is a metallized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array c a 360x a b c d e f g h j k l m n p r t b 0.3 a 0.15 b u w v 123456 78 9 10111213141516 1718 1 9 0.2 2x c a1 corner b 0.2 2x d e e3 e2 e1 e4 d2 d4 d3 d1 capacitor region 1 a 0.15 a 0.35 a a a1 a2 a3 millimeters dim min max a 2.72 3.20 a1 0.80 1 a2 1.10 1.30 a3 ? 0.6 b 0.82 0. 9 3 d 25 bsc d1 ? 11.3 d2 8 ? d3 ? 6.5 d4 9 .2 9 .4 e 1.27 bsc e 25 bsc e1 ? 11.3 e2 8 ? e3 ? 6.5 e4 7.2 7.4 e
34 5387b?hirel?07/05 pc7447a [preliminary] 12. substrate capacitors fo r the pc7447a, 360 hitce figure 12-1 shows the connectivity of the substrate capacitor pads for the pc7447a, 360 hitce. all capacitors are 100 nf. figure 12-1. substrate bypass capacitors for the pc7447a, 360 hitce 13. system design information this section provides system and thermal design recommendations for successful application of the pc7447a. 13.1 pll configuration the pc7447a pll is configured by the pll_cfg[0:4 ] signals. for a given sysclk (bus) fre- quency, the pll configuration signals set the internal cpu and vco frequency of operation. the pll configuration for the pc7447a is shown in table 13-1 on page 35 for a set of example frequencies. in this example, shaded cells represent settings that, for a given sysclk fre- quency, result in core and/or vco frequencies that do not comply with the 1400 mhz column in table 9-2 on page 25 . when enabled, dynamic frequency switching (dfs) also affects the core frequency by halving the bus-to-core multiplier; see section ?dynamic frequency switching (dfs)? on page 17 for more information. 1 c1-2 c1-1 c2-1 c3-1 c4-1 c5-1 c6-1 c6-2 c5-2 c4-2 c3-2 c2-2 c18-1 c18-2 c17-2 c16-2 c15-2 c14-2 c13-2 c13-1 c14-1 c15-1 c16-1 c17-1 c12-1 c12-2 c11-2 c10-2 c9-2 c8-2 c7-2 c7-1 c8-1 c9-1 c10-1 c11-1 c19-2 c19-1 c20-1 c21-1 c22-1 c23-1 c24-1 c24-2 c23-2 c22-2 c21-2 c20-2 a1 corner c1 gnd v dd c2 gnd v dd c3 gnd ov dd c4 gnd v dd c5 gnd v dd c6 gnd v dd c7 gnd v dd c8 gnd v dd c9 gnd v dd c10 gnd v dd c11 gnd v dd c12 gnd v dd c13 gnd v dd c14 gnd v dd c15 gnd v dd c16 gnd ov dd c17 gnd v dd c18 gnd ov dd c19 gnd ov dd c20 gnd v dd c21 gnd ov dd c22 gnd v dd c23 gnd ov dd c24 gnd v dd capacitor pad number -1 -2
35 5387b?hirel?07/05 pc7447a [preliminary] note that when dfs is enabled the resulting core frequency must meet the minimum core fre- quency requirements described in table 9-2 on page 25 . table 13-1. pc7447a microprocessor pll configuration example for 1420-mhz parts pll_cfg[0:4] example bus-to-core frequency in mhz (vco frequency in mhz) bus-to-core multiplier core-to-vco multiplier bus (sysclk) frequency 33.33 mhz 50 mhz 66.66 mhz 75 mhz 83 mhz 100 mhz 133.33 mhz 166.66 mhz 01000 2x 2x 10000 3x 2x 10100 4x 2x 667 (1333) 10110 5x 2x 667 (1333) 835 (1670) 10010 5.5x 2x 733 (1466) 919 (1837) 11010 6x 2x 600 (1200) 800 (1600) 1002 (2004) 01010 6.5x 2x 650 (1300) 866 (1730) 1086 (2171) 00100 7x 2x 700 (1400) 931 (1862) 1169 (2338) 00010 7.5x 2x 623 (1245) 750 (1500) 1000 (2000) 1253 (2505) 11000 8x 2x 600 (1200) 664 (1328) 800 (1600) 1064 (2128) 1336 (2672) 01100 8.5x 2x 638 (1276) 706 (1412) 850 (1700) 1131 (2261) 1417 (2833) 01111 9x 2x 600 (1200) 675 (1350) 747 (1494) 900 (1800) 1197 (2394) 01110 9.5x 2x 633 (1266) 712 (1524) 789 (1578) 950 (1900) 1264 (2528) 10101 10x 2x 667 (1333) 750 (1500) 830 (1660) 1000 (2000) 1333 (2667) 10001 10.5x 2x 700 (1400) 938 (1876) 872 (1744) 1050 (2100) 1397 (2793) 10011 11x 2x 733 (1466) 825 (1650) 913 (1826) 1100 (2200) 00000 11.5x 2x 766 (532) 863 (1726) 955 (1910) 1150 (2300) 10111 12x 2x 600 (1200) 800 (1600) 900 (1800) 996 (1992) 1200 (2400) 11111 12.5x 2x 600 (1200) 833 (1666) 938 (1876) 1038 (2076) 1250 (2500)
36 5387b?hirel?07/05 pc7447a [preliminary] notes: 1. pll_cfg[0:4] settings not listed are reserved. 2. the sample bus-to-core frequencies show n are for reference only. some pll configurations may select bus, core, or vco frequencies that are not useful, not supported, or not tested for by the pc7455; see section ?clock ac specifications? on page 25 for valid sysclk, core, and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly and the pll is disabled. however, the bus interface unit requires a 2x clock to function. therefore, an additional signal, ext_qual, must be driven at one-half the frequency of sysclk and offset in phase to meet the required input se tup tivkh and hold time tixkh (see table 9-3 on page 27 ). the result will be that the processor bus frequency will be one-half sysclk while the internal processor is clocked at sysclk frequency. this mode is intended for factory use and emulator tool use only. note: the ac timing specifications given in th is document do not apply in pll-bypass mode. 4. in pll-off mode, no clocking occurs inside the pc7447a regardless of the sysclk input. 01011 13x 2x 650 (1300) 865 (1730) 975 (1950) 1079 (2158) 1300 (2600) 11100 13.5x 2x 675 (1350) 900 (1800) 1013 (2026) 1121 (2242) 1350 (2700) 11001 14x 2x 700 (1400) 933 (1866) 1050 (2100) 1162 (2324) 1400 (2800) 00011 15x 2x 750 (1500) 1000 (2000) 1125 (2250) 1245 (2490) 11011 16x 2x 800 (1600) 1066 (2132) 1200 (2400) 1328 (2656) 00001 17x 2x 850 (1900) 1132 (2264) 1275 (2550) 1411 (2822) 00101 18x 2x 600 (1200) 900 (1800) 1200 (2400) 1350 (2700) 00111 20x 2x 667 (1334) 1000 (2000) 1332 (2664) 01001 21x 2x 700 (1400) 1050 (2100) 1399 (2797) 01101 24x 2x 800 (1600) 1200 (2400) 11101 28x 2x 933 (1866) 1400 (2800) 00110 pll bypass pll off, sysclk clocks core circuitry directly 11110 pll off pll off, no core clocking occurs table 13-1. pc7447a microprocessor pll configuration example for 1420-mhz parts (continued)
37 5387b?hirel?07/05 pc7447a [preliminary] 13.2 pll power supply filtering the av dd power signal is provided on the pc7447a to provide power to the clock generation pll. to ensure stability of the internal clock, th e power supplied to the av dd input signal should be filtered of any noise in the 500 khz to 10 mhz resonant frequency range of the pll. a circuit similar to the one shown in figure 13-1 using surface mount capacitors with minimum effective series inductance (esl) is recommended. the circuit should be placed as close as possible to the av dd pin to minimize noise coupled from nearby circuits. it is often possible to route directly from the capacitors to the av dd pin, which is on the periphery of the 360 hitce footprint. figure 13-1. pll power supply filter circuit 13.3 decoupling recommendations due to the pc7447a dynamic power management feature, large address and data buses, and high operating frequencies, the pc7447a can generate transient power surges and high fre- quency noise in its power supply, especially while driving large c apacitive loads. this noise must be prevented from reaching other components in the pc7447a system, and the pc7447a itself requires a clean, tightly regulated source of power. therefore, it is recommended that the sys- tem designer use sufficient decoupling capaci tors, typically one capacitor for every 1-2 v dd pins, and a similar or lesser amount for the ov dd pins, placed as close as possible to the power pins of the pc7447a. it is also recommended that these decoupling capacitors receive their power from separate v dd , ov dd , and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should have a value of 0.01 or 0.1 f. only ceramic surface mount technology (smt) capacitors should be used to minimize lead inductance. orientations where connections are made along the length of the part, such as 0204, are preferable but not mandatory. consis- tent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993) and contrary to previous recommendations for decoupling freescale microprocessors, multiple small capacitors of equal value are recom- mended over using multiple values of capacitance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd and ov dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a lo w equivalent series resistance (esr) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors are: 100-330 f (avx tps tantalum or sanyo oscon). 13.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropri- ate signal level. unless otherwise noted, unused active low inputs should be tied to ov dd , and unused active high inputs should be connected to gnd. all nc (no connect) signals must remain unconnected. v dd 10 ? 2.2 f 2.2 f gnd av dd low esl surface mount capacitors
38 5387b?hirel?07/05 pc7447a [preliminary] power and ground connections must be made to all external v dd , ov dd , and gnd pins in the pc7447a. for backward compatibility with th e pc7447 to the pc7447a, th e new power and ground signals (formerly nc, see table 8-1 on page 21 ) may be left unconnected. there is no performance degradation associated with leaving these pins unconnected. however, future devices may require these additional power and ground signal s to be connected to achieve maximum perfor- mance, and it is recommended that new designs include the additional connections to facilitate future upgrades. see also section ?pinout listings? on page 21 for additional information. 13.5 output buffer dc impedance the pc7447a processor bus drivers are characterized over process, voltage, and temperature. to measure z 0 , an external resistor is connected from the chip pad to ov dd or gnd. the value of each resistor is varied until the pad voltage is ov dd /2. figure 13-2 on page 38 shows the driver impedance measurement. the output impedance is the average of two components?the resistances of the pull-up and pull- down devices. when data is held low, sw2 is closed (sw1 is open), and r n is trimmed until the voltage at the pad equals ov dd /2. r n then becomes the resistance of the pull-down devices. when data is held high, sw1 is closed (sw2 is open), and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. figure 13-2. driver impedance measurement table 13-2 summarizes the signal impedance results. the impedance increases with junction temperature and is relatively unaffected by bus voltage. table 13-2. impedance characteristics with v dd = 1.5v, ov dd = 1.8v 5%, t j = 5 - 85 c impedance processor bus l3 bus unit z 0 typical 33 ? 42 34 ? 42 ? maximum 31 ? 51 32 ? 44 ? ov dd ognd sw2 sw1 rn rp pad data
39 5387b?hirel?07/05 pc7447a [preliminary] 13.6 pull-up/pull-down resistor requirements the pc7447a requires high-resistive (weak: 4.7-k ? ) pull-up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the pc7447a or other bus masters. these pins are: ts , artry , shdo , and shd1 . some pins designated as being factory test pins must be pulled up to ov dd or down to gnd to ensure proper device operation. for the pc7447a, 360 bga, the pins that must be pulled up to ov dd are lssd_mode and test[0:3]; the pins that must be pulled down to gnd are: l1_tstclk and test[4]. the ckstp_in signal should likewise be pulled up through a pull-up resistor (weak or stronger: 4.7?1 k ? ) to prevent erroneous assertions of this signal. in addition, the pc7447a has one open-drain style ou tput that requires a pull-up resistor (weak or stronger: 4.7?1 k ? ) if it is used by the system. this pin is ckstp_out . if pull-down resistors are used to configure bvsel, the resistors should be less than 250 ? (see table 8-1 on page 21 ). because pll_cfg[0:4] must remain stable during normal operation, strong pull-up and pull-down resistors (1 k ? or less) are recommended to configure these sig- nals in order to protect against erroneous sw itching due to ground bounce, power supply noise or noise coupling. during inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. because the pc7447a must continually monitor t hese signals for snooping, this float condition may cause excessive power draw by the input re ceivers on the pc7447a or by other receivers in the system. these signals can be pulled up through weak (10-k ? ) pull-up resistors by the system, address bus driven mode enabled (see the mpc7450 risc microprocessor family users? manual for more information on this mode), or they may be otherwise driven by the sys- tem during inactive periods of the bus to avoid this additional power draw. preliminary studies have shown the additional power draw by the pc7447a input receivers to be negligible and, in any event, none of these measures are necessary for proper device operation. the snooped address and transfer attribute inputs are: a[0:35], ap[0:4], tt[0:4], ci , wt , and gbl . if address or data parity is not used by the system, and respective parity checking is disabled through hid1, the input receivers for those pins are disabled and do not require pull-up resistors, and may be left unconnected by the system. if extended addressing is not used (hid0[xaen] = 0), a[0:3] are unused and must be pulled low to gnd through weak pull-down resistors; addi- tionally, if address parity che cking is enabled (hid1[eba] = 1) and extended addr essing is not used, ap[0] must be pulled up to ov dd through a weak pull-up resistor. if the pc7447a is in 60x bus mode, dti[0:3] must be pulled low to gnd through weak pull-down resistors. the data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-u p resistors on the bus. other data bu s receivers in the system, however, may require pull-ups, or that those signals be otherwis e driven by the system during inactive periods by the system. the data bus signals are: d[0:63] and dp[0:7].
40 5387b?hirel?07/05 pc7447a [preliminary] 13.7 jtag configuration signals boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification but is pr ovided on all processors that implement the powerpc architecture. while it is possible to force the tap controller to the reset state using only the tck and tms signals, mo re reliable power-on reset performance will be obtained if the trst signal is asserted during power-on reset. be cause the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these proces sors allows a remote computer system (typically a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signal s. the cop port requires the ability to indepen- dently assert hreset or trst in order to fully control the processor. if the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 13-3 on page 41 allows the cop port to independently assert hreset or trst , while ensuring that the target can drive hreset as well. if the jtag inter- face and cop header will not be used, trst should be tied to hreset through a 0 ? . isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during power-on. although freescale recommends that the cop header be designed into the system as shown in figure 13-3 on page 41 , if this is not pos- sible, the isolation resistor will allow future access to trst in the case where a jtag interface may need to be wired onto the system in debug situations. the cop header shown in figure 13- 3 on page 41 adds many benefits?breakpoints, watc hpoints, register and memory examina- tion/modification, and other standard debugger features are possible through this interface?and can be as inexpensive as an unpopulated fo otprint for a header to be added when needed. the cop interface has a standard header for connection to the target system, based on the 0.025 inch square-post, 0.100 inch centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. there is no standardized way to number the cop header shown in figure 13-3 on page 41 ; con- sequently, many different pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number th e pins counter clockwise from pin 1 (a s with an ic). regardless of the num- bering, the signal placement recommended in figure 13-3 on page 41 is common to all known emulators. the qack signal shown in figure 13-3 on page 41 is usually connected to the pci bridge chip in a system and is an input to the pc7447a informing it that it can go into the quiescent state. under normal operation this occurs during a low-power mode selection. in order for cop to work, the pc7447a must see this signal as serted (pulled down). while shown on the cop header, not all emulator products drive this signal. if the product does not, a pull-down resistor can be populated to assert this signal. additio nally, some emulator products implement open- drain type outputs and can only drive qack asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is negated when it is not being driven by the tool. note that the pull-up and pull-down resistors on the qack signal are mutually exclusive and it is never neces- sary to populate both in a system. to preserve correct power-down operation, qack should be merged through logic so that it also can be driven by the pci bridge.
41 5387b?hirel?07/05 pc7447a [preliminary] figure 13-3. jtag interface connection notes: 1. run/stop , normally found on pin 5 of the cop header, is not implemented on the pc7447a. connect pin 5 of the cop header to ov dd with a 10 k ? pull-up resistor. 2. key location; pin 14 is not physi cally present on the cop header. 3. component not populated. populate only if debug tool does not drive qack . 4. populate only if debug tool uses an open-drain type output and does not actively de-assert qack . 5. if the jtag interface is implemented, connect hreset from the target source to trst from the cop header though an and gate to trst of the part. if the jtag interface is not imple- mented, connect hreset from the target source to trst of the part through a 0 ? isolation resistor. 6. the cop port and target board should be able to independently assert hreset and trst to the processor in order to fully control the processor as shown above. hreset hreset (6) hreset 13 sreset sreset sreset 11 vdd_sense 6 5 (1) 15 2 k ? 10 k ? 10 k ? 10 k ? ov dd ov dd ov dd ov dd chkstp_in chkstp_in 8 tms tdo tdi tck tms tdo tdi tck 9 1 3 4 trst 7 16 2 10 14 (2) key qack ov dd ov dd ov dd trst (6) 10 k ? 10 k ? 10 k ? 10 k ? ov dd qack qack chkstp_out chkstp_out 3 13 9 5 1 6 10 2 15 11 7 16 12 8 4 key no pin cop connector physical pin out 10 k ? (4) ov dd ov dd 1 2 k ? (3) 0 ? (5) 12 nc nc from target board sources (if any) cop header 10 k ?
42 5387b?hirel?07/05 pc7447a [preliminary] 14. package mechanical data the following sections provide the package par ameters and mechanical dimensions for the hitce package. 14.1 package parameters fo r the pc7447a, 360 hitce the package parameters are as provided in the following list. the package type is 25 25 mm, 360-lead high coefficient of the thermal expansion ceramic ball grid array (hitce). package outline 25 mm 25 mm interconnects 360 (19 19 ball array - 1) pitch 1.27 mm (50 mil) minimum module height 2.72 mm maximum module height 3.24 mm ball diameter 0.89 mm (35 mil) 15. ordering information note: 1. for availability of the different versions, contact your local atmel sales office. 16. definitions 16.1 life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. atmel customers using or selling these prod ucts for use in such applicatio ns do so at their own risk and agree to fully indemnify atmel for any damages resulting from such improper use or sale. pc 7447a v gh 1000 lx prefix ty p e revision level (1) rev. b application modifier (1) l: 1.3v 50 mv n: 1.1v 50 mv max internal processor speed (1) 1000 mhz (n-spec) 1167 mhz (n-spec) tbc 1333 mhz (l-spec) 1420 mhz (l-spec) tbc temperature range: t j (1) prototype (x) v: -40?c, 110?c m: -55?c +125?c package gh: hitce
43 5387b?hirel?07/05 pc7447a [preliminary] 17. document revision history table 17-1 provides a revision history fo r this hardware specification. table 17-1. document revision history revision number date substantive change(s) b 07/05 changed die size table 9-2 on page 25 : modified jitter specifications to conform to jedec standards, changed jitter specification to cycle-to-cycle ji tter (instead of long- and short-term jitter); changed jitter bandwidth recommendations. added t khtsv , t kharv , t khtsx , and t kharx to table 9-3 on page 27 ; these were previously grouped with t khov and t khox . note: documentation change only; the values for the output valid and output hold ac timing specifications remain unchanged for ts , artry , and shd [0:1]. a 04/04 initial revision
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